Main circuit elements, types, and features of VD (voltage detector) | NEXTY Electronics, an electronic components and semiconductor trading company

As the name suggests, a VD (voltage detector) is a product that monitors voltage.
They are also called voltage detectors, voltage monitoring ICs, reset ICs, etc.
Last time, we introduced the main uses of VDs (voltage detectors).
This time, we will introduce the main circuit elements of VDs (voltage detectors) and the features of each type, although not all of them are included.

Internal blocks and main circuit elements of VD

Output driver type (CMOS/open drain)

There are two types of reset IC output formats: N MOS FETS open drain and CMOS.
The choice of which to use depends on whether the POWER SUPPLIES POWER SUPPLIES voltage of the reset IC is the same as that of the microcontroller receiving the reset signal.
If the reset IC and the microcontroller share the same POWER SUPPLIES system, CMOS output can be used.
In the case of a separate POWER SUPPLIES system, an N MOS FETS open-drain output is used. The open-drain output makes it possible to set the optimum input voltage for the microcontroller by pulling up the output TERMINALS to the I/O POWER SUPPLIES of the microcontroller.

	N MOS FETS open drain output (Nch open drain output)	CMOS output
Block Diagram
Circuit location	Can be used in a variety of circuits	Can be used in circuits with fixed signal specifications
merit	The output voltage can be set to the pull-up voltage within the rated range. Multiple outputs can be ORed.	No external components are required for output. Low power consumption as almost no current flows even in the reset (detection) state.
Disadvantages	Requires a pull-up resistor on the output. Current flows through the pull-up resistor during the reset (detection) state.	The input voltage of the output destination is limited.

Types and features

Separate SENSE TERMINALS type

The POWER SUPPLIES TERMINALS (VIN) of a typical reset IC has two roles: to supply the operating voltage of the IC and to monitor the voltage (VIN detection type).
A reset IC with a separate SENSE TERMINALS is a type of product that has two separate pins: TERMINALS supplies the IC's operating voltage (VDD TERMINALS) and TERMINALS that monitors the voltage (SENCE TERMINALS).

VIN detection type
Separate SENSE TERMINALS type

VIN detection type timing chart

①The VIN voltage (monitoring voltage) is greater than the detection voltage, so the reset release signal (Vout="H") is output.

②When the VIN voltage falls below the detection voltage, a reset signal (Vout="L") is output.
It remains "L" down to the IC's minimum operating voltage.

3) If the VIN voltage drops further and falls below the IC's minimum operating voltage, IC operation will become unstable or stop, and the output will become undefined.

④When the VIN voltage rises and exceeds the minimum operating voltage, the IC returns to normal operation and outputs "L" again.

⑤When the VIN voltage exceeds the release voltage, the output becomes "H" after the release delay time has elapsed.
If the latter stage is a microcontroller, it will resume normal operation.

Why is it indefinite?

When VIN falls below the minimum operating voltage, the output NMOS TRANSISTORS turns off, and the voltage pulled up by the output resistor is output. In the case of CMOS output, when the output falls below the minimum operating voltage from the "L" state, the NMOS TRANSISTORS turns off, and the output becomes a voltage close to VIN. If VIN is further reduced and falls below the threshold value of the PMOS TRANSISTORS, the output becomes high impedance and undefined. In both open-drain output and CMOS output, when VDD is between 0V and near the minimum operating voltage, the output is pulled up by VIN and floats up.

Timing chart for SENSE TERMINALS separated type

The SENSE TERMINALS separated type is suitable for circuits monitoring low voltages, as the output will not become unstable even if the input voltage to the SENSE TERMINALS is low as long as the operating POWER SUPPLIES voltage is supplied to the VDD TERMINALS.

①It is assumed that sufficient POWER SUPPLIES voltage (VDD) is applied.
Since the SENCE voltage (monitoring voltage) is greater than the detection voltage, a reset release signal (Vout="H") is output.

②When the monitored voltage falls below the detection voltage, a reset signal (Vout="L") is output.
If sufficient VDD is applied, the monitoring voltage will continue to drop, and even if it reaches around 0V, the IC will continue to operate normally and the output will remain "L".

③ When the monitoring voltage increases and exceeds the release voltage, the output becomes "H" after the release delay time has elapsed.
If the latter stage is a microcontroller, it will resume normal operation.