PLL (Phase Locked Loop) response characteristics

Loop Response Frequency

The closed feedback response characteristic can be defined by the loop response frequency fc.
The loop response frequency, fc, is equal to the loop bandwidth.
The loop response frequency fc is the frequency at which the gain becomes 0 dB when expressed in the Bode diagram of the open loop gain, and is calculated as the product of the transfer functions Kp, KF, Kv, and N in the diagram.
Loop response frequency: 2×π×fc＝(Kp×KF×2×π×Kv）/N

A higher loop response frequency results in a faster response time, but also a wider bandwidth and therefore higher phase noise.
Also, a lower loop response frequency results in lower phase noise but slower response time.

Relationship between phase margin Φ and closed feedback response characteristics

If the phase margin is not appropriate, the phase fluctuation will not converge properly and will continue to exist.
The phase margin is determined by the loop response frequency fc and the LF cutoff frequency fa.
The phase margin is also called the damping factor and is calculated as 0.5×√(2×π×fc/(2×2×π×fa)).

A higher loop response frequency results in a faster response time, but also a wider bandwidth and therefore higher phase noise.
Also, a lower loop response frequency results in lower phase noise but slower response time.

Wideband oscillation (wide frequency oscillation range)
The frequency can be set precisely
Fast frequency setting speed
Low phase noise
Fewer spurious

Many of these involve trade-offs.

Generates a frequency that is N times the reference frequency fr.

A crystal OSCILLATORS with excellent frequency stability is used for the reference frequency fr.
A VCO is an LC OSCILLATORS and is not very stable, but it can oscillate at high frequencies.
By dividing RFout with a divider 1/N, a frequency synthesizer can be configured that converts fr to RFout using a PLL.
This replaces the less stable VCO output with one that has the same frequency stability as a crystal OSCILLATORS.

If the output frequency of the VCO is RFout, the input frequency fv to the phase detector (PFD) is expressed by the following equation:
fv=RFout/N

When the PLL is configured, fv is equal to the REFin reference frequency fr, so fv = fr holds, and RFout is given by the following equation.
RFout=fr×N

The frequency is varied using a programmable divider.

The output frequency can be changed in fr steps.
If you make the divider programmable and vary the value of N, you get a frequency synthesizer that steps the output by fr.
In this way, by making the 1/N divider of a PLL frequency synthesizer programmable as a variable divider, its range of applications is greatly expanded.

An ideal PLL frequency synthesizer should have fast frequency switching times and low phase noise.

When using the integer divider 1/N, the frequency step width Δf had to be equal to the reference frequency fr.
By replacing the divider with a fractional divider, fr can be increased several times while keeping the frequency step size Δf the same.

This provides a high-speed, low-phase-noise PLL frequency synthesizer.
The frequency division number N can be reduced and the PLL loop bandwidth widened, resulting in faster frequency switching times.
In addition, since the value of the frequency division number N is small, the phase noise within the loop bandwidth can be reduced.

Fractional division achieves an equivalent fractional division ratio by changing the division ratio of the divider over time.

The diagram shows the basic configuration of fractional division.
The accumulator switches the division number to N+1 K times out of F times of the variable divider output pulse.
The FK division number will remain at N.
Therefore, the average division number is expressed by the following formula:
N_ave=[K(N+1)+(FK)N]/F=N+K/F

The fractional division N_ave=10+3/16＝10.1875 is shown in the time chart.

In one cycle (F=16), N+1 occurs 3 times and N occurs 13 times.

Important PLL response characteristics

Advances in communications technology require PLL frequency synthesizers to be able to respond quickly on the time axis.

For example, if the reference frequency fr is 200KHz and the N value of the frequency divider is changed from 1950 to 2050, RFout will change from 390MHz to 410MHz. The response characteristics at that time are shown below.

Ideal and actual response characteristics

The figure shows a conceptual diagram of the response characteristics of a PLL.
When the output frequency is RFout=390MHz, the control voltage at point A of the VCO is V1.
When N is changed to 2050, the PLL negative feedback circuit generates a control voltage V2 that sets RFout to 410MHz.
Ideally, the control voltage V1 → V2 would move linearly as shown in ①, switching from 390 MHz to 410 MHz in an instant, but in reality it does not move that way.
When we want to switch the frequency up to 410MHz by ts, we want a PLL that meets this performance, but if the design is incorrect, an overshoot like ② may occur, which could have a negative effect on adjacent channels.
Also, as in ③, it may take some time to switch to td.

Obtain the response characteristics of a PLL frequency synthesizer in time and frequency domains.

Using the PD signal as a trigger, measure the VCO voltage time domain waveform and RF spectrum waveform.
Conditions: RFout = 410MHz, fr = 200kHz, loop response frequency fc = 3KHz, phase margin Φ = 45°.

Free-run spectrum waveform before lock-on

Response characteristics of fc = 410MHz, fr = 200KHz, fc ≒ 3KHz, Φ ≒ 45°

During the PD signal low period, the charge pump output is off, so the VCO voltage is approximately 0V.
Therefore, the free-running spectrum (approximately 381 MHz) before lockup is observed.

Spectrum near the overshoot during lock-on operation

Response characteristics of fc = 410MHz, fr = 200KHz, fc ≒ 3KHz, Φ ≒ 45°

This data is taken when the PD signal is high and the overshoot voltage is near its peak during lockup operation.
You can see that the RF spectrum exceeds 410MHz and reaches around 416MHz.

Lock-on → Spectrum after 600us

Response characteristics of fc = 410MHz, fr = 200KHz, fc ≒ 3KHz, Φ ≒ 45°

This data was taken 600us after the start of lockup operation. The RF spectrum is around 410.8MHz and is not yet stable.

Lock-on → Spectrum after 1200us

Response characteristics of fc = 410MHz, fr = 200KHz, fc ≒ 3KHz, Φ ≒ 45°

This data was taken 1200us after the start of lock-on operation. The RF spectrum has converged up to 410.0MHz, and lock-up is almost complete.

Response characteristics of a PLL with severe overshoot

Next, let's consider the case where the PLL phase margin is extremely small and the loop FILTERS is calculated with Φ ≒ 15°.

The VCO voltage at the CH1 input is severely overshooting. Observing the RF spectrum around the overshoot, we can see that it is reaching around 435MHz, far exceeding the set frequency of 410MHz.
There is a possibility that it may cause interference to adjacent channels.

Response characteristics of a PLL that has experienced a cycle slip

Assuming a PLL with a reference frequency fr = 500KHz, the loop response frequency fc ≒ 3KHz and phase margin Φ ≒ 65°.

You can see a cycle slip in the VCO voltage at the CH1 input. With fr set to 500KHz, you might think it would operate faster, but due to the cycle slip, it is slower than the previous lock-up operation at fr = 200KHz.