Methods for increasing speed and reducing noise in PLL (Phase Locked Loop) | NEXTY Electronics, a trading company for electronic components and semiconductors

In the field of communications, especially mobile communications, data transfer speeds and volumes are increasing with each new generation, which in turn requires the built-in PLLs (Phase Locked Loops) to also become faster.
This column will explain "PLL basics," "PLL response characteristics," and "methods for increasing PLL speed and reducing noise" in separate articles. This time, we will provide a detailed explanation of "methods for increasing PLL speed and reducing noise."

Fast lockup mode reduces lock time

Fast Lockup Mode

To suppress reference leakage spurious, high-frequency spurious, and noise, it is necessary to use a PLL with a low loop response frequency, which means giving up fast frequency switching times.
Conversely, to achieve fast switching times, a PLL with a high loop response frequency must be used, at the expense of high-frequency spurious suppression.
However, by using the fast lockup mode, this trade-off problem can be alleviated.

The diagram below explains the operation of fast lockup mode. Here, the charge pumps CP1 and CP2 can be switched. Also, the value of R2 can be changed by connecting R2' in parallel.
CP1 is a charge pump in normal mode, with a gain Kp, and the constants of C1, C2, and R2 are determined as a PLL with a low loop response frequency. CP2 is a charge pump in fast lockup mode, with a gain Kpb set larger than Kp.

Set the phase margin Φ to an appropriate value

The charge pump selects CP2 and by increasing the gain Kpb, the open loop gain of the PLL increases and the loop response frequency fc moves to a higher frequency range, widening the loop bandwidth.
However, this alone will reduce the phase margin Φ, leading to instability and degraded response characteristics.
Therefore, in fast lockup mode, it is effective to change the value of R2 to operate at an appropriate Φ value.

The figure shows an example of open-loop characteristics in normal mode and fast-lock mode.
In this example, the gain Kpb is set so that the bandwidth of the fastlock mode is 10 times that of the normal mode (B=10). The value of R2' is also selected so that the phase margin Φ does not change.

Evaluating the response characteristics of fast lockup

In fast lock mode, it operates at high speed as a PLL with a wide loop bandwidth, and when it approaches the target frequency, it returns to normal mode with a narrow bandwidth PLL.
The figure shows the actual response characteristics of the fast lockup mode, evaluated in the time domain using a spectrum analyzer as the zero span.

Compared to normal mode, the response time can be significantly reduced, and spurious and phase noise can be kept the same as normal mode.

Fast Lockup Mode Design Procedure

The design procedure for fast lockup mode is shown below.

1. Calculate the loop FILTERS constant in the normal mode narrow band.
2. The output current of the charge pump CP1 in normal mode is set to a low value.
3. Find Kpb to make the fast lockup mode wideband, and set a large output current at CP2.
4. Find R2' to make the first lockup mode broadband.
5. Verify the open loop characteristics and phase characteristics.
6. In fast lock mode, the PLL operates at high speed as a wide loop bandwidth PLL, and when it approaches the target frequency, it returns to the narrow bandwidth PLL of normal mode, but this time can be selected.