PLL (Phase Locked Loop) Basics

In the field of communications, especially mobile communications, data transfer speeds and volumes are increasing with each new generation, which in turn requires the built-in PLLs (Phase Locked Loops) to also become faster.
In this column, we will explain "PLL basics," "PLL response characteristics," and "methods for increasing the speed and reducing noise of PLLs" in separate installments.
This time, we will explain the basics of PLL.

How PLLs are used

PLLs are used as signal sources for frequency conversion in wireless communications.

This is a block diagram of the receiver section of the radio.
The RF frequency is input to the mixer, and then down-converted to the IF band by inputting the Lo1 and Lo2 frequencies.
The PLL circuit generates Lo1 and Lo2.

OTHERS is also used as a clock source for AD/DA inside a microcontroller, a bit timing generator, and for jitter cleaning.
If a PLL were not used, the desired frequency could be generated by multiplying quartz crystal unit, but if there were multiple desired frequencies, it would be necessary to install multiple quartz crystal unit, which would increase the circuit size.In addition, multiple frequencies can be generated by creating an oscillator circuit called a VFO (Variable Frequency Oscillator) using L (coil) and C (CAPACITORS), but it is not possible to generate a constant frequency due to environmental changes such as temperature.

Basic configuration of PLL

The basic configuration of a typical PLL is shown below.

The diagram shows the most basic PLL, which consists of the following components:

1. VCO: Voltage Controlled OSCILLATORS
2. N: Divider (variable frequency divider)
3. PFD: Phase Frequency Detector
4. CP: Charge Pump
5. LF: Loop FILTERS

A PLL frequency synthesizer uses a phase comparator to compare the phase of the signal fv, which is the VCO oscillation frequency divided by a divider, with the reference frequency fr, and controls the VCO frequency and phase so that they match, resulting in the VCO oscillation frequency RFout.

How the frequency is kept constant

How does a PLL work?

Due to environmental changes, the VCO frequency has become fr<fv or fr>fv.
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The phase detector PFD compares it with fr and generates an error signal pulse at the output.
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It passes through the loop FILTERS LF and becomes a DC voltage Vt.
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The DC voltage Vt controls the VCO to lower or raise the frequency.
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The VCO frequency changes, returning it to the fr = fv state.

PLL is a great device that acts as an automatic control circuit

Explanation of each part

Phase Comparator and Charge Pump

InA receives the fr pulse wave, and InB receives the fv pulse wave.
A PFD (phase detector) compares the phases of two input signals and outputs the difference.
The charge pump (CP) outputs a voltage (or current) proportional to the phase difference of the phase comparator.

The average pulse amount of the CP output is proportional to the phase difference.

The figure above shows the output of the CP. The pulse average amount is proportional to the phase difference, and a current/phase is output, which is called the phase comparison sensitivity kp.
The transfer function obtained is kp=mA/rad (current/phase).

Loop FILTERS determines closed feedback response characteristics

Loop FILTERS image that determines the closed feedback response characteristics

LF is called the loop FILTERS, and is a block that converts the output of CP into the VCO control voltage Vt.
The phase comparator pulse output is converted into a VCO control voltage Vt.
It is basically an LPF with compensated phase characteristics.
The transfer function obtained is KF ⇒ V/mA (voltage/current).

VCO that generates high-frequency signals

The output frequency is controlled by the VCO control voltage Vt.
The closer the input/output characteristics are to a straight line, the easier it is to design a PLL.
The transfer function is Kv = Hz/V (frequency/voltage).