An interface that transcends media limitations and enables flexible connections | What is xMII?

What is xMII (Media Independent Interface)?

There are many types of PHYs, and the appropriate PHY is selected based on the intended use, such as communication speed and distance. MII is used to transmit information between various PHYs and MAC. 100BASE-T1 for automotive Ethernet is defined as a 15m 1-pair UTP CABLES with a communication speed of 100Mbps, while 1000BASE-TX for consumer Ethernet is defined as a 100m CAT6 CABLES with a communication speed of 1Gbps.
For details on various PHYs, see What is Automotive Ethernet (Technical Column)?
Even if the PHY is replaced and implemented on a circuit board, it can still communicate with the MAC via the MII.

• What is Automotive Ethernet? (Technical Column)

MII signal

The communication lines consist of 16 lines: clock lines (TX_CLK, RX_CLK), delimiter lines (TX_EN, RX_DV), data lines (TXD, RXD), error lines (TX_ER, RX_ER), and media status lines (CRS, COL). Two management lines (MDC, MDIO) are used to read and write register values.

Clock Line

• TX_CLK

The PHY provides a clock signal that serves as the transmission timing reference for the TX_EN, TXD, and TX_ER signals.
It provides a TX_CLK frequency of 2.5 MHz when operating at 10 Mb/s and a TX_CLK frequency of 25 MHz when operating at 100 Mb/s.

• RX_CLK

The PHY provides a clock signal that serves as the transmission timing reference for the RX_DV, RXD, and RX_ER signals.
Like TX_CLK, it provides a TX_CLK frequency of 2.5 MHz when operating at 10 Mb/s and a TX_CLK frequency of 25 MHz when operating at 100 Mb/s.

Delimiter Line

• TX_EN

This signal indicates that data is present on the TXD line and operates based on TX_CLK.
It remains asserted while transmitting data on the TXD line.

• RX_DV

This signal indicates that data is present on the RXD line and operates based on RX_CLK.
It remains asserted while transmitting data on the RXD line.

Data Line

• TXD〈3:0〉

The MAC sends data divided into 4-bit FRAMES to the PHY. TXD[0] indicates the least significant bit.
Like TX_EN, it operates based on TX_CLK, and when TX_EN is asserted, data is read from PYH every TX_CLK period.
However, no data is read into PYH when TX_EN is deasserted.

• RXD〈3:0〉

PHY transmits data by dividing FRAMES into 4-bit chunks. RXD[0] indicates the least significant bit.
Like RX_DV, it operates based on RX_CLK, and when RX_DV is asserted, data is read by the MAC every RX_CLK period.
However, no data is read by the MAC when RX_DV is deasserted.

Error Line

• TX_ER

It operates based on TX_CLK and functions when TX_EN is asserted.
If TX_ER is asserted, it indicates that the packet is an error packet.

• RX_ER

It operates based on RX_CLK and functions when RX_DV is asserted.
If RX_ER is asserted, it indicates that the packet is an error packet.

Media Status Line

• CRS

Detects whether data is being sent to the transmission medium.
CRS is asserted when either the transmit or receive medium is not idle, and is deasserted when both are idle.
It remains asserted even during data collisions.
It does not operate relative to TX_CLK or RX_CLK.

• COL

Detects data collisions on the transmission medium.
COL is asserted when a collision is detected and remains asserted for the duration of the collision.
It does not operate relative to TX_CLK or RX_CLK.

Management Line

• MDC

The MAC provides a clock signal that serves as the reference for the transmission timing of the MDIO signal.
Regardless of the timing of TX_CLK and RX_CLK, the minimum high and low times of MDC are 160 ns each, and the minimum period of MDC is 400 ns.

• MDIO

It communicates bidirectionally between PHY and MAC, transmitting control and status information.
For more information on MDIO, see What is MDIO? (Technical Column).

• What is MDIO (Technical Column)

Differences between each xMII

RMII

The major difference compared to MII is the reduction in the number of pins, which has led to an increase in clock frequency, unification of clock lines, and inclusion of specific line functions.

GMII

The biggest difference between GMII and MII is that the data transmission and reception speed is now 1Gbps, which means that the number of data lines and clock frequency have increased.

RGMII

The major difference compared to GMII, which communicates at 1Gbps, is the reduced number of pins, along with the inclusion of double data rate (DDR) clock frequency and specific line functions.
However, for 10/100Mbps, the clock frequency is Single Data Rate (SDR).

SGMII

Two data signals and two CLK signals are used to carry FRAMES data and link rate information between the 10/100/1000 PHY and the Ethernet MAC.
The data signal operates at 1.25 Gbaud and the CLK operates at 625 MHz (DDR IF).
The traditional GMII data signals (TXD/RXD), data valid signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are encoded, serialized, and output with the appropriate DDR CLK.